A semiconductor chip, commonly known as a Large-Scale Integrated (LSI) circuit, consists of complementary metal-oxide-semiconductor field-effect transistors (CMOS), comprising both positive-type and negative-type transistors. CMOS devices are continually miniaturized year by year. Presently, state-of-the-art LSI chips integrate billions of transistors, transforming their structure from a 2-dimensional planar type to 3-dimensional gate-all-around structures. Amid the era of the increasingly complex CMOS manufacturing processes described above, the CMOS Integration team is focused on creating groundbreaking technologies which are applicable to a few chip generations at Super Clean Room in AIST-WEST, Tsukuba.
This schematic illustrates the typical structure of a gate-all-around (GAA) nanosheet CMOS in a 2-nanometer chip technology. Within this design, you can find a couple of nanosheets through which either electrons or holes run. These ultrathin ribbons are surrounded by the metal gate electrode (MG) and the high-k gate dielectric beneath the MG. Recently, we have introduced a variety of state-of-the-art manufacturing tools for advanced lithography, selective epitaxial growth, atomic-layer deposition, and highly selective etching. We are developing advanced process technologies for GAA nanosheet CMOS by leveraging these workhorses.
Extarnal website:Super Clean Room(SCR)