AIST：Semiconductor Frontier Research Center　National Institute of Advanced Industrial Science and Technology

3D Integration Technology Research TeamAbout

Higher performance by 3DIC technology.

We are conducting research and development on building an integrated circuit design platform with a chiplet structure and increasing the scale of superconducting quantum computing systems by applying 3DIC technology. Manufacturing of through-Si via (TSV), narrow pitch bump formation, and direct bonding are also developed as our core technology. In addition to these fabrication techniques, we are also researching electrical and thermal analysis and electrical, evaluation and reliability.

3D Integration Technology Research TeamResearch Topic

3-D integration employing direct bonding

Planer interface pads are activated and bonded within vacuum condition. This technology arrows room temperature bonding of two materials.

Narrow pitch bump formation

Our original technique to form cone-shaped bump enables extremely small and narrow pitch interconnect.

Development of design platform for chiplet based IC module

We investigate process technologies including interposer, bump, and integration to develop integration technology of chiplet.

3DIC technology for quantum computer and quantum annealer

We develop low temperature bonding technology to protect fragile qubits and direct bonding technology between superconductive materials.

Development of backside buried metal (BBM)

Thick metal pattern with TSV is buried onto a large area which was never used before. The buried metal provides drastic improvement of power integrity of 3DIC.

3D Integration Technology Research TeamFacility

Deep reactive ion etching system

This machine forms TSV via-hole by accurate controlling etching gas.

Wafer bonding system

It enables wafer-bonding in vacuum after precision wafer alignment.

Flip-chip bonder

bonding machine for chip to chip bonding, with various parameters including load and temperature while bonding.

Nanoparticle deposition (NPD) system

Cone-shaped bump can be fabricated with self-formation, by spraying nanoparticles using carrier gas.

Reliability evaluation systems

Thermal cycle test (TCT), high accelerated stress test (HAST), and constant temperature and humidity test chambers enables various types of reliability test.

3D Integration Technology Research TeamTeam Members

KIKUCHI Katsuya: TeamLeader
ARAGA Yuuki
FUJINO Masahisa
WATANABE Naoya
SHIMAMOTO Haruo: Invited Senior Researcher