Outline of Super Clean Room Facility (SCR)

Super cleanroom

• Floor area: 3,000 m²
• Cleanliness: Class 3 (JIS B 9920, ISO 14644-1)
• Wafer size: 12-inch wafer support
• Based on CMOS technology utilizing ArF immersion lithography

Cleanroom environment

• Temperature and humidity: 23±1°C 45±5% FFU (fine filter unit) with unidirectional flow
• Chemical contamination control: 4-layer cross-section on one side, airlock, and chemical filter
• Vibration control: Foundation improvement, mat slab, expansion joint, and concrete slab flooring in places

The super cleanroom (SCR) provides process equipment for the fabrication of general-purpose semiconductor integrated circuits using 300 mm silicon wafers. Research and development, as well as individual process modules and stand-alone processes can be performed utilizing the process menu shown below.

We also provide support for development of new techniques by offering advice on the use of pre-cleaning and contamination control.

*Processes currently available

• Processes for passive Si-Photonics components (300 mm wafers)
• Bulk & SOI 65 nm transistor processes (300 mm wafers)
• 45 nm 2-layer copper wiring processes (300 mm wafers)