ナノCMOS集積グループ / Nano CMOS Integration Group

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研究成果/ Results

2019 論文発表

1 K. Ono, T. Mori, and S. Moriyama,”High-temperature operation of a silicon qubit”, Scienctific Reports, 9, (2019), 469 https://doi.org/10.1038/s41598-018-36476-z

2018 学会発表

11 S. Migita, H. Ota, and A. Toriumi,“Assessment of Steep-Subthreshold Swing Behaviors in Ferroelectric-Gate Field-Effect Transistors Caused by Positive Feedback of Polarization Reversal”, Internation Electron Device Meeting (IEDM), San Francisco, USA, December 2018 https://doi.org/10.1109/IEDM.2018.8614485
10 Y. Morita, T. Maeda, T. Matsukawa, and K. Endo,“AFM measurement of layer-by-layer Ge etching by active oxidation for scaled Ge device application”, ACSIN-14 & ICSPM26, Sendai, Japan, October 2018
9 I. Akita, and T. Okazawa,“Mixed-domain analog frontend circuit design for power-efficient multi-channel sensor systems”, IEEE 2018 Int. Conf. on Advanced Technology for Commutations (ATC), Ho ChiMinh, Vietnum, October 2018
8 S. Migita,“Apprehension of Large Coersive Field in Ferroelectric HfO2 Thin Films”, AiMES2018, ECS and SMEQ Joint International Meeting, in symposium "Semiconductors, Dilectric and Metals for Nanoelectronics 16", Cancun, Mexico, October 2018
7 S. Migita, H. Ota, K. Shibuya, H. Yamada, A. Sawa, T. Matsukawa, and A. Toriumi,“Phase Transformation Kinetics of Hf-Zr-O Thin Films Examined through Wide Ranges of Annealing Temperature and Annealing Time”, 2018 International Conference on Solid-State Devices and Materials (SSDM), Tokyo, Japan, September 2018
6 S. Migita, H. Ota, H. Yamada, K. Shibuya, A. Sawa, T. Matsukawa, and A. Toriumi,“Voltage Scaling in HfO2-based Ferroelectric-Gate Field-Effect Transistors Using Metal/Ferroelectric/Metal/Insulator/Semiconductor Structure”, 2018 IEEE Silicon Nanoelectronics Workshop, Honolulu, USA, July 2018
5 S. O'uchi, H. Fuketa, T. Ikegami, W. Nogami, T. Matsukawa, T. Kudoh, and R. Takano,“Image-Classifier Deep Convolutional Neural Network Training by 9-Bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format”, IEEE International Symposium on Circuits & Systems (ISCAS2018), Florence, Italy, May 2018, https://doi.org/10.1109/ISCAS.2018.8350953
4 T. Matsukawa,“Process challenges for further scaling of FinFETs (Invited)”, Emerging Technology 2018, Whistler, Canada, May 2018
3 T. Mori,“ON-current boosting technology for silicon tunnel field-effect transistors (Invited)”, NANOTECH Malaysia 2018, Kuala Lumpur, Malaysia, May 2018
2 T. Matsukawa, T. Mori, Y. Sawada, Y. Kinoshita, Y. Liu, and M. Masahara ,“Damageless and Conformal Doping for FinFETs by Spin-Coated Phosphorus Doped Silica”, International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA2018), Hsinchu, Taiwan, Apr. 2018
1 S. Migita, H. Ota, H. Yamada, K. Shibuya, A. Sawa, T. Matsukawa, and A. Toriumi,“Ion Implantation Synthesis of Si-Doped HfO2 Ferroelectric Thin Films”, Electron Devices Technology and Manufacturing Conference (EDTM2018), Kobe, Japan, Feb. 2017

2018 論文発表

4 T. Mori, Y. Morita, and T. Matsukawa,”Effect of post-implantation annealing on Al?N isoelectronic trap formation in silicon: Al?N pair formation and defect recovery mechanisms ”, AIP Advances, 8, (2018), p. 055024,  https://aip.scitation.org/doi/10.1063/1.5030795
3 森 貴洋, “SトンネルFETを用いた超低消費電力集積回路”,応用物理 87, (2017), p. 04CB01 http://www.jsap.or.jp/ap/2018/04/ob870262.html
2 T. Mori, H. Asai, K. Fukuda, and T. Matsukawa,”Process and device integration for silicon tunnel FETs utilizing isoelectronic trap technology to enhance the ON current”, Japanese Journal of Applied Physics, 57, (2018), p. 04FA04  https://doi.org/10.7567/JJAP.57.04FA04
1 S. Migita, H. Ota, H. Yamada, K. Shibuya, A. Sawa, and A. Toriumi,”Polarization switching behavior of Hf-Zr-O ferroelectric ultrathin films studied through coercive field characteristics”, Japanese Journal of Applied Physics, 57, (2018), p. 04FB01 https://doi.org/10.7567/JJAP.57.04FB01

2017 学会発表

7 S. Migita, H. Ota, H. Yamada, K. Shibuya, A. Sawa, T. Matsukawa, and A. Toriumi,“Synthesis of Si-doped HfO2 Ferroelectric Thin Films using Silicon Ion Implantation”, 48th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, USA, Dec. 2017
6 S. Migita“Relationship between Ferroelectricity and Electrical Breakdown in Hf-Zr-O Thin Films (Invited)”, 232nd ECS Meeting, Maryland, USA, 2017
5 S. Migita, H. Ota, H. Yamada, K. Shibuya, A. Sawa, and A. Toriumi,“Polarization Switching Behavior of HfO2-based Ferroelectric Ultrathin Films Studied through Coercive Field Characteristics”, Int’l Conf. Solid State Device and Materials (SSDM2017), Sendai, Japan, pp.541-542, 2017
4 T. Mori, H.Asai and T. Matsukawa,“Improvement of Device and Circuit Performance of Si-based Tunnel Field-Effect Transistors by Utilizing Isoelectronic Trap Technology (Invited)”, Int’l Conf. Solid State Device and Materials (SSDM2017), Sendai, Japan, pp.239-240, 2017
3 S. Migita, H. Ota, H. Yamada, A. Sawa and A. Toriumi,“Coincident Increment of Ferroelectrocity and Leakage Current Emerged in Metal-Composition-Controlled Hf-Zr-O system”, Silicon Nanoelectronics Workshop (SNW2017), Kyoto, Japan, 2017
2 T. Mori,“ON Current Boosting Technology for Si-based Tunnel Field-Effect Transistors Utilizing Isoelectronic Trap”, 2017 MRS Spring Meeting, Phoenix, USA, 2017
1 S. Migita, H. Ota, H. Yamada, A. Sawa and A. Toriumi,“Thickness-Independent Behavior of Coercive Field in HfO2-based Ferroelectrics”, Electron Devices Technology and Manufacturing Conference (EDTM2017), Toyama, Japan, 2017, https://doi.org/10.1109/EDTM.2017.7947587

2017 論文発表

9 T. Mori, S. Iizuka and T. Nakayama,”Material engineering for silicon tunnel field-effect transistors: isoelectronic trap technology”, MRS Communications, 7, (2017) p.541, https://doi.org/10.1557/mrc.2017.63
8 T. Matsukawa, Y. Liu, T. Mori, Y. Morita, S. Otsuka, S. O'uchi, H. Fuketa, S. Migita and M. Masahara,”Impact of residual defects caused by extension ion implantation in FinFETs on parasitic resistance and its fluctuation”, Solid-State Electronics, 132, (2017), p.103, http://doi.org/10.1016/j.sse.2017.03.014
7 H. Fuketa, S. O’uchi and T. Matsukawa, “A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25, (2017), p. 2007, https://doi.org/10.1109/TVLSI.2017.2677978
6 H. Fuketa, S. O’uchi and T. Matsukawa, “Fully Integrated, 100-mV Minimum Input Voltage Converter With Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting”, IEEE Transactions on Circuits and Systems II: Express Briefs, 64, (2017), p. 392, https://doi.org/10.1109/TCSII.2016.2573382
5 Y. Morita, K. Fukuda, Y. Liu, T. Mori, W. Mizubayashi, S. O’uchi, H. Fuketa, S. Otsuka, S. Migita, M. Masahara, K. Endo, H. Ota and T. Matsukawa, “Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application”, Japanese Journal of Applied Physics 56, (2017), p. 04CD19 https://doi.org/10.7567/JJAP.56.04CD19
4 T. Mori, S. Migita, K. Fukuda, H. Asai, Y. Morita, W. Mizubayashi, Y. Liu, S. O’uchi, H. Fuketa, K. Fukuda, S. Otsuka, T. Yasuda, M. Masahara, H. Ota and T. Matsukawa, “Suppression of tunneling rate fluctuations in tunnel field-effect transistors by enhancing tunneling probability”, Japanese Journal of Applied Physics 56, (2017), p. 04CD02 https://doi.org/10.7567/JJAP.56.04CD02
3 S. Otsuka, T. Mori, Y. Morita, N. Uchida, Y. Liu, S. O’uchi, H. Fuketa, S. Migita, M. Masahara and T. Matsukawa, “Structural and electrical characterization of epitaxial Ge thin films on Si(001) formed by sputtering”,Japanese Journal of Applied Physics 56, (2017), p. 04CB01 https://doi.org/10.7567/JJAP.56.04CB01
2 S. Otsuka, T. Mori, Y. Morita, N. Uchida, Y. Liu, S. O'uchi, H. Fuketa, S. Migita, M. Masahara, T. Matsukawa,”Epitaxial growth of Ge thin film on Si (001) by DC magnetron sputtering”, Materials Science in Semiconductor Processing, 70, (2017), p. 3  http://dx.doi.org/10.1016/j.mssp.2016.09.012
1 H. Fuketa, S. O'uchi, T. Matsukawa,”A 0.3-V 1-uW Super-Regenerative Ultrasound Wake-Up Receiver with Power Scalability”, IEEE Transactions on Circuits and Systems II: Express Briefs, 64, (2017), p. 1027 http://dx.doi.org/10.1109/TCSII.2016.2621772

2016 学会発表

6 S. Migita, H. Ota, H. Yamada, A. Sawa, and A. Toriumi,”Drawback of Large Coercive Fields in HfO2-based Ferroelectric Thin Films from the Standpoint of Dielectric Breakdown”, IEEE Semiconductor Interface Specialists Conference (SISC), San Diego, USA, 2016
5 T. Mori, H. Asai, J. Hattori, K. Fukuda, S. Otsuka, Y. Morita, S. O'uchi, H. Fuketa, S. Migita, W. Mizubayashi, H. Ota, T.Matsukawa,Demonstrating Performance Improvement of Complementary TFET Circuits by ION Enhancement Based on Isoelectronic Trap Technology”,  Int'l Electron Device Meeting (IEDM2016), pp.512-515, 2016 http://dx.doi.org/10.1109/IEDM.2016.7838453
4 T. Mori, S. Migita, K. Fukuda, H. Asai, Y. Morita, W. Mizubayashi, Y. Liu, S. O'uchi, H. Fuketa, S. Otsuka, T. Yasuda, M. Masahara, H. Ota, T.Matsukawa,”On the Variability of Tunnel Field-Effect Transistors: Suppression of BTBT Fluctuation by Tunneling Probability Enhancement”, Int’l Conf. Solid State Devices and Materials (SSDM2016), Tsukuba, Japan, pp.51-52, 2016
3 Y. Morita, K. Fukuda, Y. Liu, T. Mori, W. Mizubayashi, S. O'uchi, H. Fuketa, S. Otsuka, S. Migita, M. Masahara, K. Endo, H. Ota, T. Matsukawa, “Tunnel FinFET CMOS Inverter with Very Low Short-Circuit Current for Ultra-Low Power IoT Application”, Int’l Conf. Solid State Devices and Materials (SSDM2016), Tsukuba, Japan, pp.49-50, 2016
2 S. Otsuka, T. Mori, Y. Morita, N. Uchida, Y. Liu, S .O’uchi1, H. Fuketa, S. Migita, M. Masahara, T. Matsukawa, “Structural and Electrical Characterization of Epitaxial Ge Thin Film on Si (001) Formed by Sputtering”, Int’l Conf. Solid State Devices and Materials (SSDM2016), Tsukuba, Japan, pp.645-646, 2016
1 S. Otsuka, T. Mori, Y. Morita, N. Uchida, Y. Liu, S. O’uchi, H. Fuketa, S. Migita, M. Masahara, T. Matsukawa ,“Epitaxial Growth of Ge Thin Film on Si (001) by DC Magnetron Sputtering”, ISCSI-VII and ISTDM2016, Hiroshima, Japan, pp.77-78, 2016

2016 論文発表

3 Y. Morita, K. Fukuda, T. Mori, W. Mizubayashi, S. Migita, K. Endo, S. O’uchi, Y.X. Liu, M. Masahara, T. Matsukawa, and H. Ota, “Introduction of SiGe/Si heterojunction into novel multilayer tunnel FinFET”, Japanese Journal of Applied Physics 55, (2016), p. 04EB06 http://doi.org/10.7567/JJAP.55.04EB06
2 H. Fuketa, S. O’uchi, K. Fukuda, T. Mori, Y. Morita, M. Masahara, and T. Matsukawa, “Closed-form analytical model of static noise margin for ultra-low voltage eight-transistor tunnel FET static random access memory”, Japanese Journal of Applied Physics 55, (2016), p. 04ED06 http://doi.org/10.7567/JJAP.55.04ED06
1 T. Matsukawa, Y.X. Liu, T. Mori, Y. Morita, S. O’uchi, S. Otsuka, S. Migita, and M. Masahara, “Impact of extension implantation conditions of fin field-effect transistors on gate-induced drain leakage”,Japanese Journal of Applied Physics 55 (2016), p. 04EB01 http://doi.org/10.7567/JJAP.55.04EB01

2015 学会発表

8 Y. Morita, T. Maeda, H. Ota, W. Mizubayashi, S. O’uchi, M. Masahara, T. Matsukawa, and K. Endo, “Novel Wafer-Scale Uniform Layer-by-Layer Etching Technology for Line Edge Roughness Reduction and Surface Flattening of 3D Ge Channels”,  Int'l Electron Device Meeting (IEDM2015), pp.390-393, 2015 http://dx.doi.org/10.1109/IEDM.2015.7409703
7 S. O’uchi, Y. Liu, Y. Hori, T. Irisawa, H. Fuketa, Y. Morita, S. Migita, T. Mori, T. Nakagawa, J. Tsukada, H. Koike, M. Masahara, and T. Matsukawa, “Robust and Compact Key Generator Using Physically Unclonable Function Based on Logic-Transistor-Compatible Poly-Crystalline-Si Channel FinFET Technology”,  Int'l Electron Device Meeting (IEDM2015), pp.648-651, 2015 http://dx.doi.org/10.1109/IEDM.2015.7409767
6 S. O’uchi, K. Endo, Y.X. Liu, T. Matsukawa, Y. Ishikawa, J. Tsukada, H. Yamauchi, W. Mizubayashi, S. Migita, Y. Morita, H. Ota, and M. Masahara, “0.8-V Rail-to-Rail Operational Amplifier with Near-Vt Gain-Boosting Stage in FinFET Technology for IoT Sensor Nodes”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, California, USA, 2015 http://dx.doi.org/10.1109/S3S.2015.7333536
5 Y. Morita, T. Mori, K. Fukuda, W. Mizubayashi, S. Migita, K. Endo, S. O’uchi, Y.X. Liu, M. Masahara, T. Matsukawa, and H. Ota, “Introduction of SiGe/Si Heterojunction into Novel Multilayer Tunnel FinFETs”, Int’l Conf. Solid State Devices and Materials (SSDM2015), Sapporo, Japan, pp.32-33, 2015
4 T. Matsukawa, Y.X. Liu, T. Mori, Y. Morita, S. O’uchi, H. Fuketa, S. Otsuka, S. Migita, and M. Masahara, “Optimization of Extension Doping Condition of FinFETs for Ultra-Low-Power Applications”, Int’l Conf. Solid State Devices and Materials (SSDM2015), Sapporo, Japan, pp.1106-1107, 2015
3 H. Fuketa, S. O'uchi, K. Fukuda, T. Mori, Y. Morita, M. Masahara, and T.Matsukawa, “Variation Analysis for Ultra-Low Voltage 8T Tunnel FET SRAM Using Closed-Form Analytical Model of Static Noise Margin”, Int’l Conf. Solid State Devices and Materials (SSDM2015), Sapporo, Japan, pp.982-983, 2015
2 Y.X. Liu, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, M. Masahara, “Highly Vt tunable and low variability triangular fin-channel MOSFETs on SOTB”, International Conference on Insulating Films on Semiconductors (INFOS), Udine, Italy, pp.290-293, 2015
1 Y.X. Liu, Y. Hori, M. Ohno, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, and M. Masahara, 2015 Int’l Symp. VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, p.TR52, 2015

2015 論文発表

7 Y.X. Liu, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, M. Masahara, “Highly Vt tunable and low variability triangular fin-channel MOSFETs on SOTB”, Microelectronic Engineering 147 (2015) p.290 http://www.sciencedirect.com/science/article/pii/S0167931715003007
6 T. Matsukawa, K. Fukuda, Y. Liu, J. Tsukada, H. Yamauchi, K. Endo, Y. Ishikawa, S. O’uchi, S. Migita, Y. Morita, W. Mizubayashi, H. Ota, and M. Masahara, “Impact of granular work function variation in a gate electrode on low-frequency noise for fin field-effect transistors”, Applied Physics Express 8, (2015), p. 044201 http://iopscience.iop.org/article/10.7567/APEX.8.044201
5 Y. Morita, T. Mori, S. Migita, W. Mizubayashi, K. Fukuda, T. Matsukawa, K. Endo, S. O’uchi, Y.X. Liu, M. Masahara, and H. Ota, “Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on performance of tunnel field-effect transistors”, Solid-State Electronics, 113 (2015) p.173 http://www.sciencedirect.com/science/article/pii/S003811011500163X
4 Y.X. Liu, T. Nabatame, N. Nguyen, T. Matsukawa, K. Endo, S. O’uchi1, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, T. Chikyow, and M. Masahara, “Channel shape and interpoly dielectric material effects on electrical characteristics of floating-gate-type three-dimensional fin channel flash memories”, Japanese Journal of Applied Physics 54, (2015), p. 04DD04  http://iopscience.iop.org/article/10.7567/JJAP.54.04DD04
3 T. Mori, K. Fukuda, N. Miyata, Y. Morita, S. Migita, W. Mizubayashi, M. Masahara, T. Yasuda, and H. Ota, “Study of gate leakage current paths in p-channel tunnel field-effect transistor by current separation measurement and device simulation”, Japanese Journal of Applied Physics 54, (2015), p. 034202 http://iopscience.iop.org/article/10.7567/JJAP.54.034202
2 T. Mori, W. Mizubayashi, Y. Morita, S. Migita, K. Fukuda, N. Miyata, T. Yasuda, M. Masahara, and H. Ota, “Effect of hot implantation on ON-current enhancement utilizing isoelectronic trap in Si-based tunnel field-effect transistors”, Applied Physics Express 8, (2015), p. 036503 http://iopscience.iop.org/article/10.7567/APEX.8.036503
1 T. Mori, Y. Morita, N. Miyata, S. Migita, K. Fukuda, W. Mizubayashi, M. Masahara, T. Yasuda, and H. Ota, “Study of tunneling transport in Si-based tunnel field-effect transistors with ON current enhancement utilizing isoelectronic trap”, Applied Physics Letters 106 (2015), p. 083501 http://scitation.aip.org/content/aip/journal/apl/106/8/10.1063/1.4913610

2014 学会発表

8 Y. Morita, T. Mori, K. Fukuda, W. Mizubayashi, S. Migita, T. Matsukawa, K. Endo, S. O’uchi, Y. Liu, M. Masahara, H. Ota, “Experimental Realization of Complementary p- and n- Tunnel FinFETs with Subthreshold Slopes of less than 60 mV/decade and Very Low (pA/μm) Off-Current on a Si CMOS Platform”, Int'l Electron Device Meeting (IEDM2014), pp.243-3246, 2014 http://dx.doi.org/10.1109/IEDM.2014.7047020
7 T. Matsukawa, K. Fukuda, Y. Liu, J. Tsukada, H. Yamauchi, Y. Ishikawa, K. Endo, S. O’uchi, S. Migita, W. Mizubayashi, Y. Morita, H. Ota, and M. Masahara, “Scaling Breakthrough for Analog/Digital Circuits by Suppressing Variability and Low-Frequency Noise for FinFETs by Amorphous Metal Gate Technology”, Int'l Electron Device Meeting (IEDM2014), pp.299-302, 2014 http://dx.doi.org/10.1109/IEDM.2014.7047035
6 Y.X. Liu, T, Nabatame, N. Nguyen, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, T. Chikyow, and M. Masahara, “Comparative Study of Floating Gate Type 3D Fin-Channel Flash Memories with Different Channel Shapes and Interpoly Dielectric Layers”, Int’l Conf. Solid State Devices and Materials (SSDM2014), Tsukuba, Japan, pp.464-465, 2014
5 S. Migita, T. Matsukawa, T. Mori, K. Fukuda, Y. Morita, W. Mizubayashi, K. Endo, Y. Liu, S. O’uchi, M. Masahara, and H. Ota, “Variation Behavior of Tunnel-FETs Originated from Dopant Concentration at Source Region and Channel Edge Configuration”, 2014 European Solid-State Device Research Conference (ESSDERC), Venice, Italy, pp.278-281, 2014 http://dx.doi.org/10.1109/ESSDERC.2014.6948814
4 Y. Morita, T. Mori, S. Migita, W. Mizubayashi, K. Fukuda, T. Matsukawa, K. Endo, S. O’uchi, Y.X. Liu, M. Masahara, and H. Ota, “Improvement of Epitaxial Channel Quality on Heavily Arsenic- and Boron-doped Si surfaces and Impact on Tunnel FET Performance”, 2014 European Solid-State Device Research Conference (ESSDERC), Venice, Italy, pp.182-185, 2014 http://dx.doi.org/10.1109/ESSDERC.2014.6948790
3 Y.X. Liu, T. Nabatame, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, T. Chikyow and M. Masahara, “Fabrication and Characterization of 3D Fin-Channel MANOS Type Flash Memory”, 2014 Silicon Nanoelectronics Workshop, Honolulu, USA, pp.69-70, 2014 http://dx.doi.org/10.1109/SNW.2014.7348559
2 T. Mori, Y. Morita, N. Miyata, S. Migita, K. Fukuda, M. Masahara, T. Yasuda, and H. Ota, “Band-to-Band Tunneling Current Enhancement Utilizing Isoelectronic Trap and its Application to TFETs”, 2014 VLSI Symposium, Honolulu, USA, pp.86-87, 2014 http://dx.doi.org/10.1109/VLSIT.2014.6894370
1 T. Matsukawa, K. Fukuda, Y.X. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. O'uchi, W. Mizubayashi, S. Migita, Y. Morita, H. Ota and M. Masahara, “Lowest Variability SOI FinFETs Having Multiple Vt by Back-Biasing”, 2014 VLSI Symposium, Honolulu, USA, pp. 142-145, 2014 http://dx.doi.org/10.1109/VLSIT.2014.6894393

2014 論文発表

3 Y.X. Liu, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, and M. Masahara, “Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates”, Japanese Journal of Applied Physics 53, (2014), p. 04ED16 http://iopscience.iop.org/article/10.7567/JJAP.53.04ED16
2 T. Matsukawa, Y.X. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. O'uchi, W. Mizubayashi, H. Ota, S. Migita, Y. Morita and M. Masahara, “Influence of work function variation of metal gates on fluctuation of sub-threshold drain current for fin field-effect transistors with undoped channels”, Japanese Journal of Applied Physics 53, (2014), p. 04EC11 http://iopscience.iop.org/article/10.7567/JJAP.53.04EC11
1 S. Migita, Y. Morita, T. Matsukawa, M. Masahara, and H. Ota, “Experimental Demonstration of Ultrashort-Channel (3 nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI”IEEE TRANSACTIONS ON NANOTECHNOLOGY, 13, (2014), pp.208-215 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6701137

2013 学会発表

9 Y.X. Liu, T. Nabatame, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, T. Chikyow, and M. Masahara, “Charge Trapping Type FinFET Flash Memory with Al2O3 Blocking Layer”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Monterey, USA, p.8a-2, 2013
8 S. Migita, Y. Morita, M. Masahara, and H. Ota, “Synthesis of Perovskite Structure SrHfO3 Thin Films on Si Substrates Using RF Sputtering and Rapid Thermal Anneal”, Int’l Conf. Solid State Electronics and Materials (SSDM2013), Fukuoka, Japan, pp.10-11, 2013
7 Y. X. Liu, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, and M. Masahara, “Experimental Study of 3D Fin-Channel Charge Trapping Flash Memories with TiN Metal and Poly-Si Gates”, Int’l Conf. Solid State Electronics and Materials (SSDM2013), Fukuoka, Japan, pp.556-557, 2013
6 T. Matsukawa, Y.X. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. O’uchi, W. Mizubayashi, H. Ota, S . Migita, Y. Morita and M. Masahara, “Influence of work function variation in a metal gate on fluctuation of current-onset voltage for undoped-channel FinFETs”, Int’l Conf. Solid State Electronics and Materials (SSDM2013), Fukuoka, Japan, pp.740-741, 2013
5 Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. O’uchi, Y.X. Liu, M. Masahara, and H. Ota “CMOS-Compatible Mesa-Etched Ultrathin Epitaxial Channel Tunnel Field-Effect Transistors”, Int’l Conf. Solid State Electronics and Materials (SSDM2013), Fukuoka, Japan, pp.748-749, 2013
4 Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. O’uchi, Y.X. Liu, M. Masahara, and H. Ota, “Performance Limit of Parallel Electric Field Tunnel FET and Improvement by Modified Gate and Channel Configurations”, 2013 European Solid-State Device Research Conference (ESSDERC), Bucharest, Romania, pp.45-48, 2013
3 Y. Morita, T. Mori, S, Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, K. Endo, S. O’uchi, Y.X. Liu, M. Masahara, and H. Ota, “Synthetic electric field tunnel FETs: drain current multiplication demonstrated by wrapped gate electrode around ultrathin epitaxial channel”,  2013 VLSI Symposium, Kyoto, Japan, pp. T236-T237, 2013 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6576658&punumber%3D6571719%26filter%3DAND%28p_IS_Number%3A6576594%29%26pageNumber%3D3
2 Y. X. Liu, T. Matsukawa, K. Endo, S. O'uchi, .I. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, and M. Masahara, “Comparative Study of TiN Meta1 Gate and Poly-Si Gate Charge-Trapping Type FinFET Flash Memories”, 2013 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp.9-10, 2013
1 T. Matsukawa, Y.X. Liu, K. Endo, W. Mizubayashi, J. Tsukada, Y. Ishikawa, H. Yamauchi, S. O’uchi, H. Ota, S. Migita, Y. Morita, and M. Masahara, “Suppressed Variability of Current-Onset Voltage of FinFETs by Improvement of Work Function Uniformity of Metal Gates”, 2013 Int’l Symp. VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, pp.80-81, 2013

2013 論文発表

4 Y.X. Liu, T. Kamei, T. Matsukawa, K. Endo1 S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, A. Ogura, and M. Masahara, “Gate Structure Dependence of Variability in Polycrystalline Silicon Fin-Channel Flash Memories”, Japanese Journal of Applied Physics 52 (2013) p.06GE01 http://iopscience.iop.org/article/10.7567/JJAP.52.06GE01
3 T. Matsukawa, Y. X. Liu, W. Mizubayashi, J. Tsukada, H. Yamauchi, K. Endo, Y. Ishikawa, S. O'uchi, H. Ota, S. Migita, Y. Morita and M. Masahara, “Suppression of threshold voltage variability of double-gate fin field-effect transistors using amorphous metal gate with uniform work function”, Applied Physics Letters 102 (2013), p. 162104 http://scitation.aip.org/content/aip/journal/apl/102/16/10.1063/1.4803040
2 Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, M. Masahara, and H. Ota, “Tunnel Field-Effect Transistor with Epitaxially Grown Tunnel Junction Fabricated by Source/Drain-First and Tunnel-Junction-Last Processes”, Japanese Journal of Applied Physics 52 (2013) p.04CC25 http://iopscience.iop.org/article/10.7567/JJAP.52.04CC25
1 H. Sakai, S. O’uchi, K. Endo, T. Matsukawa, Y.X. Liu, Y. Ishikawa, J. Tsukada, T. Nakagawa, T. Sekigawa, H. Koike, M. Masahara, and H. Ishikuro, “1/f Noise Characteristics of Fin-Type Field-Effect Transistors in Saturation Region”, Japanese Journal of Applied Physics 52 (2013) p.04CC23 http://iopscience.iop.org/article/10.7567/JJAP.52.04CC23