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Advanced Power Electronics Research Center

SiC Power Device Team
 The SiC Power Device Team promotes research and development under three themes: (1) development of ultra-low-loss SiC power devices, (2) development of elemental technology for ultra-low-loss SiC power device fabrication, and (3) assessment of reliability in SiC power devices.

Overview of Research


Related National Projects

  1. 「New Material Power Semiconductor Project for Achieving a Low-Carbon Society」

     Compared with silicon (Si), large reductions in energy consumption can be achieved with silicon carbide (SiC) power semiconductors that are used widely in inverters and other equipment for the next generation of automobiles, etc. Specifically, in this project research and development is being carried out on technology for a stable supply of large, high-quality SiC wafers and devices in the high voltage range (1〜3 kV) for use in industries such as railways. In addition to emphasizing work on green innovation through this research and development, we are aiming at generating a growth industry that takes a worldwide lead. The SiC Power Device Team is responsible for high-voltage SiC-MOSFET development.


  2. [“Innovative Silicon Carbide (SiC) Power Electronics Research for Creating a Low-Carbon Society ” Funding Program for World-Leading innovative R&D on Science and Technology ]

     In this research and development program, research and development is being carried out on fundamental technology aiming at achieving not only efficient use of electrical energy but also a reduction in environmental impact by making ultra-high-voltage SiC power semiconductors practical.
    The SiC Power Device Team is responsible for developing SiC-IGBT and SiC-PiN diodes (both in a class exceeding 10 kV) which form the nucleus of ultra-high-voltage electric power converters .


Overview of Research

IE-MOSFET(Implantation Epitaxial MOSFET)

 

  In conventional SiC vertical power MOSFETs, the channel mobility in the SiO2/SiC interface that forms the MOS gate is low; therefore, the on-resistance is much greater than hoped for. IEMOSFETs have been developed to solve this problem. Unlike the conventional structure, there has been success in both improving crystalline and reducing doping concentration for channel region by carrying out (epitaxial growth) process after ion implantation to form the MOS gate. Furthermore, an extremely low on-resistance of 1.8 mΩ・cm2 at breakdown voltage of 660 V device has been achieved by developing high mobility MOS forming technology on (000-1) carbon face. Now, development is continuing on making these practical with increased current capability, high reliability, and development of mass production technology.





FIG. 1 Structural diagram for IEMOSFET


FIG. 2 Electrical characteristics of 10A/ 1200V class IEMOSFET

SiC-BGSIT(SiC Buried Gate Static Induction Transistor)

 SiC static induction transistors (SiC-SIT) do not have an oxide film/semiconductor interface like MOSFETs; therefore, they are ideal power switching devices with both low on-resistance and high reliability. However, since it has been difficult to develop normally-off type devices that have typically been used in voltage type inverters up to now, there has been a delay in making these practical. This team has been successful in developing an ultra-low-on-resistance buried gate type SiC-SIT (SiC-BGSIT) by making use of newly developed AIST process technology. Further, this team has achieved normally-off characteristics by optimizing the device design. Currently, the team has successfully fabricated a 1200 V, 35 A (RonA = 1.8 mΩ・cm2) normally-on type and a 1000 V, 35 A (RonA = 1.8 Ω・cm2) normally-off type SiC-BGSIT.


FIG. 3 Structural diagram for SiC-BGSIT

FIG. 4 Static characteristics of normally-off type SiC-BGSIT

SiC-PiN Diode

 It is anticipated that SiC-PiN diodes will be used as ultra-low-loss power diodes in high-voltage applications (electric power distribution systems, rapid transit railways, etc.) exceeding 3 kV. To achieve devices with high breakdown voltages exceeding 3 kV, innovations are necessary in the voltage-blocking structures for junction edge. At AIST, we have been successful in developing SiC-PiN diodes with breakdown voltage exceeding 7 kV by optimizing the voltage blocking structures in conjunction with mesa structures and junction termination extension (JTE) structures. Along with using high-voltage SiC-PiN diodes developed at AIST in high-voltage high-current electric power converter prototypes in cooperative research by industry, academia and government, there is a plan for developing ultra-high-voltage (> 10 kV) SiC-PiN diodes under the Funding Program for World-Leading innovative R&D on Science and Technology based on this device structure.


FIG. 5 SiC-PiN diode structure

FIG. 6 High-voltage SiC-PiN diode static characteristics

UMOSFET

 There has been success in reducing the on-resistance in SiC-MOSFET development up to now, but since progress is being made in reducing on-resistance in competing Si devices, which have exceeded theoretical limits through the development of structures such as trench gates, IGBT, and super junctions, for the practical application of SiC we must develop the next generation of MOSFETs after the IEMOSFETs that are currently in development. UMOSFETs, which are trench gated, are being anticipated as a next generation structure capable of reducing cell pitch in comparison with planar MOSFETs; however, they have problems peculiar to SiC such as variations in characteristics due to the orientation of trench surfaces because of offset angles in substrates and the generation of high electric field in the oxide film at the bottoms of trenches. Currently, hexagonal cell UMOSFETs are being developed using vicinal substrates to solve these problems.




FIG. 7 UMOSFET electrical characteristics

Super Junction

 Targeting a further reduction in on-resistance exceeding the physical limitations of SiC, we are making progress in developing SiC-SJ devices that have super junction (SJ) structures (FIG. 8). An important feature of SJ structures is the pn junctions being arranged alternately in the lateral direction, and because of the difficulty in fabrication, there have been no previous attempts to form SJ structures using SiC. Making use of the various process technology (trench forming techniques [FIG. 9], epitaxial growth technology, ion implantation technology, etc.) cultivated at the Center up to now, we have taken up the challenge of leading the world in forming SJ structures in SiC.


FIG. 8 On-resistance reduction effect of SJ structure



FIG. 9 Formation of deep trench (t 〜7 μm )

Gate Oxide Film Forming Process

 We are developing new SiC gate oxide film forming methods with both high channel mobility and high reliability. With a cold-wall ultra-high-temperature oxidation furnace (developed in cooperation with ULVAC, Inc. and ULVAC-RIKO, Inc.), oxidation film formation at extremely high temperature of 1400℃ or higher and heat treatment in various types of the atmospheres are possible (FIG. 10). In addition, by using ultra-high concentration of ozone gas progress is being made in the development of thermal methods for forming oxide films on SiC and surface cleaning methods (joint development with Meidensha Corp.).



FIG. 10 Ultra-high-temperature cold-wall oxidation furnace

Reliability Evaluations for MOS Structures

 High-reliability SiC MOS interface structures aimed at achieving SiC power devices having MOSFET key structures are being developed. In SiC devices that are required stable operation at higher temperature and in higher electric field than Si devices, it is necessary that there is higher reliability than with Si MOS interface structures. We are aiming at establishing techniques for making SiC MOS interface structures highly reliable, and we are working on development of SiC oxide film forming processes, analysis of the insulation breakdown mechanism for SiC oxide film, and development of reliability evaluation apparatus (FIG. 11).



FIG. 11 SiC oxide film reliability evaluation apparatus




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