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Advenced Power Electronics Research Center

Epitaxial Growth Team


  We conduct the study of SiC homoepitaxial growth techniques, new structure fabrication using SiC epitaxial growth techniques and material evaluation technologies using X-ray and electron beam. SiC epitaxial layers are essential to control carrier concentration, and have a huge effect on SiC device performance because devices are fabricated in epitaxial layers. We focus on development of SiC epitaxial growth and the evaluation technologies for high reliability and low cost devices. We also address the fabrication of new structure such as super junction structure to achieve innovative devices.

Moreover, we offer our epitaxial wafers in collaboration research and MTA (Material Transfer Agreement).

CVD equipment

Overview of Research

  • Large diameter
    • Now 4-inch SiC wafer is mainstream but larger wafer is necessary to lower the wafer cost. We investigate high quality epitaxial growth on both Si-face and C-face 6-inch wafers because such wafers are becoming standard materials in the industry.

    • References
       1:C. Kudo, K. Tamura, T. Aigo, W. Ito, J. Nishio, K. Kojima, T. Ohno, MRS Symposium Proceedings Series, 1433pp.h01-02、2012/07
       2:K. Masumoto, C. Kudo, K. Tamura, J. Nishio, S. Ito, K. Kojima, T. Ohno, H. Okumura, J. Crystal Growth, 381 (2013) 139.



  • Low off-angle
    • Now 4° off-angle wafer is mainstream because step flow growth using such off-angle wafers is necessary in SiC epitaxial growth to suppress polytype inclusions. However, epitaxial growth on lower off-angle substrates is required to reduce the waste due to cutting wafers on a diagonal line and to suppress anisotropy of trench MOSFET. We found that high quality epitaxial layers with 0.3° off-angle can be grown by using C-face. This technique has been applied to development of SiC trench MOSFET. Currently, we are investigating growth of Si-face epitaxial layers with lower off-angle than 4°.  

    • References
       1:K. Kojima, H. Okumura, S. Kuroda and K. Arai, J. Crystal Growth 269, 367 (2004).
       2:K. Kojima, H. Okumura, S. Kuroda and K. Arai,Mater. Sic. Forum 483-485, 93 (2005).
       3:K. Kojima, H. Okumura, S. Kuroda and K. Arai,Chemical Vapor Deposition 12, 489 (2006).
       4:K. Kojima, S. Ito, J. Senzaki and H. Okumura, Mater. Sci. Forum645-648,99, (2010).
       5:K. Kojima, S. Ito, A. Nagata and H. Okumura, Mater. Sci. Forum 717-720,141, (2012).
       6:K. Masumoto, K. Kojima, H. Okumura,Mater. Sic. Forum740-742,193 (2013).



  • Low resistivity
    • Negative effects of SiC substrate resistance on the device performance increased because on resistance of the device became low due to the development of process techniques. Therefore, heavily doped SiC substrates are required to reduce the substrate resistance. N-type SiC crystals with resistivity of less than 10mΩcm can hardly be obtained because stacking fault density drastically increases when nitrogen doping concentration increases. In the case of P-type SiC crystals, it is hard for the resistivity to be less than hundreds mΩcm because the acceptor level of aluminum is deep of about 200 mΩcm. It is difficult to fabricate a super high-voltage device, n-channel IGBT because of lack of low-resistivity P-type substrate. We study growing the low-resistivity epitaxial layer to explore the possibility of the low-resistivity substrate.  
      We succeeded to obtain n-type epitaxial layers with several mΩcm and few stacking fault by co-doping nitrogen and aluminum. Wafer Process Team in ADPERC is trying to apply this technique to n-type bulk growth. We also succeeded to obtain p-type epitaxial layers with high aluminum concentration of 1E20cm-3 and low resistivity of 13 mΩcm by using high growth rate. Moreover, we found that the activation rate of aluminum drastically increased when the doping concentration is over 1E19cm-3.  

    • References
      1:K. Kojima, T. Kato, S. Ito, J. Kojima, F. Hirose, Y. Kito, S. Yamauch, K. Nishikawa, and A. Adachi, Mater. Sci. Forum679-680, 8 (2011)
      2:S. Ji, K. Kojima, Y. Ishida, H. Tsuchida, S. Yoshida and H. Okumura, Mater.Sci Forum 740-742, 181 (2013).
      3:S. Ji, K. Kojima, Y. Ishida, S. Saito, T. Kato, H. Tsuchida, S. Yoshida and H. Okumura, J. Crystal Growth 380, 85 (2013).


  • Filling of deep trench by epitaxial growth
    • P/N stripe super junction structure has been adopted to improve the trade-off relationship between break down voltage and on-resistance in Si devices. Si P/N stripe structure can be fabricated by using thermal diffusion of dopant that hardly caused in SiC crystals. In the case of SiC, it is necessary to fill deep trench by epitaxial growth in order to fabricate the P/N stripe structure. We optimized the filling condition and successfully filled 7 μm deep and 2 μm wide trench in cooperation with SiC Power Device Team in ADPERC.  

    • Reference
      1:K. Kojima, A. Nagata, S. Ito, Y. Sakuma, R. Kosugi and Y. Tanaka, Mater. Sci. Forum740-742, 793 (2013).